ECE seminar series: Reliable and Secure Cryptographic Hardware and Deeply Embedded Systems

Thursday, February 28, 2013 ( 1:30 pm to 2:30 pm )

Location: Room 110 Altorfer Building

Contact: 
Yi Guo (yguo1@stevens.edu)

Reliable and Secure Cryptographic Hardware and Deeply Embedded Systems 

BY Mehran Mozaffari Kermani

Postdoctoral Research Fellow

Princeton University

 

ABSTRACT

Computing platforms are expected to be deeply embedded within physical objects, including human body, creating an Internet of Things. These embedded computing platforms enable a wide spectrum of applications, including implantable and wearable medical devices, smart homes, smart meters, physical infrastructure monitoring, and near-field communication (NFC) or radio-frequency identification (RFID)-based emerging applications. The explosion in devices and connectivity creates a much larger attack surface, hence opening up new opportunities for malicious attacks and, therefore, requiring effective implementations of cryptographic primitives. Not only do the implementations of cryptographic hardware and embedded systems face challenges in terms of efficiency, energy-awareness, and high performance in platforms such as application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA), but they also need to be immune to natural defects and malicious side-channel fault attacks.

In this talk, we address both these challenges in order to realize lightweight and efficient cryptographic hardware systems and also realize them to counteract the accidental and malicious faults aiming at deriving the secret keys. Through exhaustive search, the nonlinear S-boxes within the Advanced Encryption Standard (AES) – the current symmetric-key standard – are benchmarked on ASIC to reach the highest efficiency. In order to realize high-throughput and efficient VLSI implementations of authentication and ensure low-latency and efficient crypto-hardware for this standard, we propose augmenting the confidentiality guaranteed by the AES and implementing efficient and parallel VLSI architectures of the Galois/counter mode (GCM). In addition, we present several novel fault diagnosis schemes for the hardware implementations of the AES and our recent research results on lightweight/green cryptographic hardware (a new state-of-the-art measure for extremely resource-constrained applications). These techniques are benchmarked on recent Xilinx FPGAs and standard-cell ASICs and have been simulated to assess their error coverage, which is close to 100%. The proposed approaches result in more reliable and efficient architectures for cryptographic hardware, suitable for implementation on deeply embedded applications.

 

BIOGRAPHY

Mehran Mozaffari Kermani received the B.Sc. degree in electrical and computer engineering from the University of Tehran in 2005, and the M.E.Sc. and Ph.D. degrees from the Department of Electrical and Computer Engineering at the University of Western Ontario in 2007 and 2011, respectively. After the completion of his Ph.D., he joined the Advanced Micro Devices (AMD) as a senior ASIC/layout designer, designing and integrating sophisticated security/cryptographic capabilities into a single Accelerated Processing Unit. Currently, he is a postdoctoral research fellow at the Electrical Engineering Department of Princeton University. His research interests include emerging security/cryptographic measures for embedded systems, hardware systems security, fault diagnosis and tolerance in cryptographic hardware and embedded systems, and low-power secure and efficient FPGA and ASIC designs.