ECE seminar series: Low Latency and High Throughput VLSI Architectures of CORDIC Algorithm
Wednesday, December 4, 2013 – ( 3:00 pm to 4:00 pm )
Location: Babbio Center, Room 319
Low Latency and High Throughput VLSI Architectures of CORDIC Algorithm
BY Dr. Lakshmi Boppana
Department of Electronics and Communication Engineering
National Institute of Technology, Warangal, India
The current research in the design of high speed VLSI architectures for real-time Digital Signal Processing (DSP) algorithms has been directed by the advances in the VLSI technology, which have provided the designers with significant impetus for porting algorithm into architecture. Many of the algorithms used in DSP and matrix arithmetic require elementary functions such as trigonometric, inverse trigonometric, logarithmic, exponential, multiplication and division functions. These elementary functions can be efficiently implemented using processing elements performing vector rotations. The COordinate Rotation DIgital Computer (CORDIC) algorithm computes the elementary functions in a rather simple and elegant manner. CORDIC computes two dimensional vector rotation or angle of a vector using a set of iterative equations employing simple addition and shift operations. Due to the simplicity of the operations involved, the CORDIC algorithm is well suited for VLSI implementation.
During the last 50 years of the CORDIC algorithm, a wide variety of applications such as biomedical signal processing, neural networks, digital communications, 3D graphics and kinematic processing, to mention a few, have emerged. Although CORDIC may not be the fastest technique to perform these operations, it is attractive due to its potential for efficient and low cost implementation of a large class of applications. Several modifications have been proposed in the literature for the CORDIC algorithm during the last two decades to provide high performance and low cost hardware solutions for real time computation of two dimensional vector rotation and transcendental functions. In view of the requirements for high speed CORDIC, we have realized a few low latency and high throughput architectures. These architectures are regular and scalable, making them efficient for VLSI implementation. The latency and area of the proposed architectures are computed analytically in terms of full adder delay and area, respectively, to facilitate the implementation of the architecture using any technology through the selection of appropriate logic style for full adder. In addition, the latency and area of the proposed architectures are compared with other unfolded architectures available in the literature for rotational CORDIC. The functionality of the proposed architectures are verified by FPGA implementation using Xilinx design tools and also synthesized using Synopsys design compiler.
Dr. Boppana Lakshmi has obtained B.Tech (E.C.E) from Nagarjuna university, M.Tech (EI) from NIT, Warangal, and Ph.D (VLSI Architectures) from I.I.T, Kharagpur. She is working as a faculty member in National Institute of Technology, Warangal since 1990. She has done a few modules in the area of VLSI Design in England, UK in 1994. Her research interests are in the areas of Digital System Design, Microprocessor Systems, and VLSI Architectures. She regularly serves as a peer reviewer for Elsevier journals in VLSI area. Prof. Lakshmi has served as the Head of the Department of ECE, NIT, Warangal in addition to the various responsibilities held in the department. Currently, she is the principal investigator for two research projects funded by at ANURAG, DRDO, Hyderabad and RCI, Hyderabad. Prof. Lakshmi is the advisor of three doctoral students.